Commit ef84970d authored by Robert Dietrich's avatar Robert Dietrich

added perfgroup files for zen2

parent c8a1ad38
SHORT Branch prediction miss rate/ratio
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PMC2 RETIRED_BRANCH_INSTR
PMC3 RETIRED_MISP_BRANCH_INSTR
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
Branch rate PMC2/PMC0
Branch misprediction rate PMC3/PMC0
Branch misprediction ratio PMC3/PMC2
Instructions per branch PMC0/PMC2
LONG
Formulas:
Branch rate = RETIRED_BRANCH_INSTR/RETIRED_INSTRUCTIONS
Branch misprediction rate = RETIRED_MISP_BRANCH_INSTR/RETIRED_INSTRUCTIONS
Branch misprediction ratio = RETIRED_MISP_BRANCH_INSTR/RETIRED_BRANCH_INSTR
Instructions per branch = RETIRED_INSTRUCTIONS/RETIRED_BRANCH_INSTR
-
The rates state how often on average a branch or a mispredicted branch occurred
per instruction retired in total. The branch misprediction ratio sets directly
into relation what ratio of all branch instruction where mispredicted.
Instructions per branch is 1/branch rate.
SHORT Data cache miss rate/ratio
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PMC2 DATA_CACHE_ACCESSES
PMC3 DATA_CACHE_REFILLS_ALL
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
data cache requests PMC2
data cache request rate PMC2/PMC0
data cache misses PMC3
data cache miss rate PMC3/PMC0
data cache miss ratio PMC3/PMC2
LONG
Formulas:
data cache requests = DATA_CACHE_ACCESSES
data cache request rate = DATA_CACHE_ACCESSES / RETIRED_INSTRUCTIONS
data cache misses = DATA_CACHE_REFILLS_ALL
data cache miss rate = DATA_CACHE_REFILLS_ALL / RETIRED_INSTRUCTIONS
data cache miss ratio = DATA_CACHE_REFILLS_ALL / DATA_CACHE_ACCESSES
-
This group measures the locality of your data accesses with regard to the
L1 cache. Data cache request rate tells you how data intensive your code is
or how many data accesses you have on average per instruction.
The data cache miss rate gives a measure how often it was necessary to get
cache lines from higher levels of the memory hierarchy. And finally
data cache miss ratio tells you how many of your memory references required
a cache line to be loaded from a higher level. While the# data cache miss rate
might be given by your algorithm you should try to get data cache miss ratio
as low as possible by increasing your cache reuse.
SHORT Cycles per instruction
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PMC2 RETIRED_UOPS
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] PMC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
CPI (based on uops) PMC1/PMC2
IPC PMC0/PMC1
LONG
Formulas:
CPI = CPU_CLOCKS_UNHALTED/RETIRED_INSTRUCTIONS
CPI (based on uops) = CPU_CLOCKS_UNHALTED/RETIRED_UOPS
IPC = RETIRED_INSTRUCTIONS/CPU_CLOCKS_UNHALTED
-
This group measures how efficient the processor works with
regard to instruction throughput. Also important as a standalone
metric is RETIRED_INSTRUCTIONS as it tells you how many instruction
you need to execute for a task. An optimization might show very
low CPI values but execute many more instruction for it.
SHORT Load to store ratio
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PMC2 LS_DISPATCH_LOADS
PMC3 LS_DISPATCH_STORES
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
Load to store ratio PMC2/PMC3
LONG
Formulas:
Load to store ratio = LS_DISPATCH_LOADS/LS_DISPATCH_STORES
-
This is a simple metric to determine your load to store ratio.
SHORT Divide unit information
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PMC2 DIV_OP_COUNT
PMC3 DIV_BUSY_CYCLES
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
Number of divide ops PMC2
Avg. divide unit usage duration PMC3/PMC2
LONG
This performance group measures the average latency of divide operations
SHORT Power and Energy consumption
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
PWR0 RAPL_CORE_ENERGY
PWR1 RAPL_PKG_ENERGY
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
Energy Core [J] PWR0
Power Core [W] PWR0/time
Energy PKG [J] PWR1
Power PKG [W] PWR1/time
LONG
Formula:
Power Core [W] RAPL_CORE_ENERGY/time
Power PKG [W] RAPL_PKG_ENERGY/time
-
Ryzen implements the RAPL interface previously introduced by Intel.
This interface enables to monitor the consumed energy on the core and package
domain.
It is not documented by AMD which parts of the CPU are in which domain.
SHORT Double Precision MFLOP/s
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 RETIRED_SSE_AVX_FLOPS_DOUBLE_FMA
PMC2 RETIRED_MMX_FP_INSTR_ALL
PMC3 RETIRED_SSE_AVX_FLOPS_DOUBLE_ADD_MULT_DIV
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC0/PMC0
DP MFLOP/s (scalar assumed) 1.0E-06*(PMC3+(PMC2/2)+(PMC1*2))/time
DP MFLOP/s (SSE assumed) 1.0E-06*(PMC3+PMC2+(PMC1*2))/time
DP MFLOP/s (AVX assumed) 1.0E-06*(PMC3+(PMC2*2)+(PMC1*2))/time
LONG
Formulas:
CPI = INST_RETIRED_ANY/ACTUAL_CPU_CLOCK
DP MFLOP/s (scalar assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_DOUBLE_ADD_MULT_DIV + (RETIRED_MMX_FP_INSTR_ALL/2)+(RETIRED_SSE_AVX_FLOPS_DOUBLE_FMA*2))/time
DP MFLOP/s (SSE assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_DOUBLE_ADD_MULT_DIV + RETIRED_MMX_FP_INSTR_ALL+(RETIRED_SSE_AVX_FLOPS_DOUBLE_FMA*2))/time
DP MFLOP/s (AVX assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_DOUBLE_ADD_MULT_DIV + (RETIRED_MMX_FP_INSTR_ALL*2)+(RETIRED_SSE_AVX_FLOPS_DOUBLE_FMA*2))/time
-
Profiling group to measure double precisision FLOP rate. The Zen architecture
does not provide distinct events for SSE and AVX FLOPs. Moreover, scalar FP
instructions are counted as SSE instruction in RETIRED_MMX_FP_INSTR_ALL.
Therefore, you have to select the DP MFLOP/s metric based on the measured code.
SHORT Single Precision MFLOP/s
EVENTSET
FIXC0 INST_RETIRED_ANY
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 RETIRED_SSE_AVX_FLOPS_SINGLE_FMA
PMC2 RETIRED_MMX_FP_INSTR_ALL
PMC3 RETIRED_SSE_AVX_FLOPS_SINGLE_ADD_MULT_DIV
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC1/PMC0
SP MFLOP/s (scalar assumed) 1.0E-06*(PMC3+(PMC2/2)+(PMC1*4))/time
SP MFLOP/s (SSE assumed) 1.0E-06*(PMC3+(PMC2*2)+(PMC1*4))/time
SP MFLOP/s (AVX assumed) 1.0E-06*(PMC3+(PMC2*4)+(PMC1*4))/time
LONG
Formulas:
CPI = INST_RETIRED_ANY/ACTUAL_CPU_CLOCK
SP MFLOP/s (scalar assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_SINGLE_ADD_MULT_DIV + (RETIRED_MMX_FP_INSTR_ALL/2)+(RETIRED_SSE_AVX_FLOPS_SINGLE_FMA*4))/time
SP MFLOP/s (SSE assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_SINGLE_ADD_MULT_DIV + (RETIRED_MMX_FP_INSTR_ALL*2)+(RETIRED_SSE_AVX_FLOPS_SINGLE_FMA*4))/time
SP MFLOP/s (AVX assumed) = 1.0E-06*(RETIRED_SSE_AVX_FLOPS_SINGLE_ADD_MULT_DIV + (RETIRED_MMX_FP_INSTR_ALL*4)+(RETIRED_SSE_AVX_FLOPS_SINGLE_FMA*4))/time
-
Profiling group to measure single precisision FLOP rate. The Zen architecture
does not provide distinct events for SSE and AVX FLOPs. Moreover, scalar FP
instructions are counted as SSE instruction in RETIRED_MMX_FP_INSTR_ALL.
Therefore, you have to select the SP MFLOP/s metric based on the measured code.
SHORT Instruction cache miss rate/ratio
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 ICACHE_FETCHES
PMC2 ICACHE_L2_REFILLS
PMC3 ICACHE_SYSTEM_REFILLS
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC1/PMC0
L1I request rate PMC1/PMC0
L1I miss rate (PMC2+PMC3)/PMC0
L1I miss ratio (PMC2+PMC3)/PMC1
LONG
Formulas:
L1I request rate = ICACHE_FETCHES / RETIRED_INSTRUCTIONS
L1I miss rate = (ICACHE_L2_REFILLS + ICACHE_SYSTEM_REFILLS)/RETIRED_INSTRUCTIONS
L1I miss ratio = (ICACHE_L2_REFILLS + ICACHE_SYSTEM_REFILLS)/ICACHE_FETCHES
-
This group measures the locality of your instruction code with regard to the
L1 I-Cache.
SHORT Main memory bandwidth in MBytes/s (experimental)
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
DFC0 DATA_FROM_LOCAL_DRAM_CHANNEL
DFC1 DATA_TO_LOCAL_DRAM_CHANNEL
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI PMC1/PMC0
Memory read bandwidth [MBytes/s] 1.0E-06*(DFC0)*(4.0/num_numadomains)*64.0/time
Memory read data volume [GBytes] 1.0E-09*(DFC0)*(4.0/num_numadomains)*64.0
Memory write bandwidth [MBytes/s] 1.0E-06*(DFC1)*(4.0/num_numadomains)*64.0/time
Memory write data volume [GBytes] 1.0E-09*(DFC1)*(4.0/num_numadomains)*64.0
Memory bandwidth [MBytes/s] 1.0E-06*(DFC0+DFC1)*(4.0/num_numadomains)*64.0/time
Memory data volume [GBytes] 1.0E-09*(DFC0+DFC1)*(4.0/num_numadomains)*64.0
LONG
Formulas:
Memory read bandwidth [MBytes/s] = 4.0E-06*(DATA_FROM_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0/runtime
Memory read data volume [GBytes] = 4.0E-09*(DATA_FROM_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0
Memory write bandwidth [MBytes/s] = 4.0E-06*(DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0/runtime
Memory write data volume [GBytes] = 4.0E-09*(DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0
Memory bandwidth [MBytes/s] = 4.0E-06*(DATA_FROM_LOCAL_DRAM_CHANNEL+DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0/runtime
Memory data volume [GBytes] = 4.0E-09*(DATA_FROM_LOCAL_DRAM_CHANNEL+DATA_TO_LOCAL_DRAM_CHANNEL)*(4.0/num_numadomains)*64.0
-
Profiling group to measure memory bandwidth drawn by all cores of a socket.
Since this group is based on Uncore events it is only possible to measure on a
per socket base.
Even though the group provides almost accurate results for the total bandwidth
and data volume, the read and write bandwidths and data volumes seem off.
The metric formulas contain a correction factor of (4.0/num_numadomains) to
return the value for all 4 memory controllers in NPS1 mode. This is probably
a work-around. Requested info from AMD.
SHORT TLB miss rate/ratio
EVENTSET
FIXC1 ACTUAL_CPU_CLOCK
FIXC2 MAX_CPU_CLOCK
PMC0 RETIRED_INSTRUCTIONS
PMC1 DATA_CACHE_ACCESSES
PMC2 L1_DTLB_MISS_ANY_L2_HIT
PMC3 L1_DTLB_MISS_ANY_L2_MISS
METRICS
Runtime (RDTSC) [s] time
Runtime unhalted [s] FIXC1*inverseClock
Clock [MHz] 1.E-06*(FIXC1/FIXC2)/inverseClock
CPI FIXC1/PMC0
L1 DTLB request rate PMC1/PMC0
L1 DTLB miss rate (PMC2+PMC3)/PMC0
L1 DTLB miss ratio (PMC2+PMC3)/PMC1
L2 DTLB request rate (PMC2+PMC3)/PMC0
L2 DTLB miss rate PMC3/PMC0
L2 DTLB miss ratio PMC3/(PMC2+PMC3)
LONG
Formulas:
L1 DTLB request rate DATA_CACHE_ACCESSES / RETIRED_INSTRUCTIONS
L1 DTLB miss rate (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/RETIRED_INSTRUCTIONS
L1 DTLB miss ratio (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/DATA_CACHE_ACCESSES
L2 DTLB request rate (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)/RETIRED_INSTRUCTIONS
L2 DTLB miss rate L1_DTLB_MISS_ANY_L2_MISS / RETIRED_INSTRUCTIONS
L2 DTLB miss ratio L1_DTLB_MISS_ANY_L2_MISS / (L1_DTLB_MISS_ANY_L2_HIT+L1_DTLB_MISS_ANY_L2_MISS)
-
L1 DTLB request rate tells you how data intensive your code is
or how many data accesses you have on average per instruction.
The DTLB miss rate gives a measure how often a TLB miss occurred
per instruction. And finally L1 DTLB miss ratio tells you how many
of your memory references required caused a TLB miss on average.
NOTE: The L2 metrics are only relevant if L2 DTLB request rate is
equal to the L1 DTLB miss rate!
SHORT PIKA metric group 1
EVENTSET
PMC0 RETIRED_INSTRUCTIONS
PMC1 CPU_CLOCKS_UNHALTED
METRICS
ipc PMC0/PMC1
LONG
Power Core [W] RAPL_CORE_ENERGY/time
Power PKG [W] RAPL_PKG_ENERGY/time
-
Ryzen implements the RAPL interface previously introduced by Intel.
This interface enables to monitor the consumed energy on the core and package
domain.
It is not documented by AMD which parts of the CPU are in which domain.
Ignoring PWR0 RAPL_CORE_ENERGY for now
Perf does not provide rapl_power for zen2 yet
PWR0 RAPL_CORE_ENERGY
PWR1 RAPL_PKG_ENERGY
rapl_power (PWR0+PWR1)/time
Memory Bandwidth works currently only for the NPS1 setting.
DFC0 DATA_FROM_LOCAL_DRAM_CHANNEL
DFC1 DATA_TO_LOCAL_DRAM_CHANNEL
mem_bw (DFC0+DFC1)*(4.0/num_numadomains)*64.0/time
SHORT PIKA metric group 2
EVENTSET
PMC0 RETIRED_MMX_FP_INSTR_ALL
PMC1 RETIRED_SSE_AVX_FLOPS_SINGLE_FMA
PMC2 RETIRED_SSE_AVX_FLOPS_SINGLE_ADD_MULT_DIV
PMC3 RETIRED_SSE_AVX_FLOPS_DOUBLE_FMA
PMC4 RETIRED_SSE_AVX_FLOPS_DOUBLE_ADD_MULT_DIV
METRICS
flops_any (PMC2+(PMC0/2)+(PMC1*4)+PMC4+(PMC3*2))/time
LONG
--
Scalar is assumed for FLOPS
SP FLOP/s (scalar assumed) (PMC2+(PMC0/2)+(PMC1*4))/time
SP FLOP/s (SSE assumed) (PMC2+(PMC0*2)+(PMC1*4))/time
SP FLOP/s (AVX assumed) (PMC2+(PMC0*4)+(PMC1*4))/time
DP FLOP/s (scalar assumed) (PMC4+(PMC0/2)+(PMC3*2))/time
DP FLOP/s (SSE assumed) (PMC4+PMC0+(PMC3*2))/time
DP FLOP/s (AVX assumed) (PMC4+(PMC0*2)+(PMC3*2))/time
-
flops_sp (PMC2+(PMC0/2)+(PMC1*4))/time
flops_dp (PMC4+(PMC0/2)+(PMC3*2))/time
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